1. Field of the Invention
The present invention relates to an apparatus for analyzing a failure for a semiconductor memory device.
2. Description of the Related Art
Conventionally, a memory test method using BIST (Built-in Self Test) has been widely used as a method for analyzing a failure of a memory for a semiconductor memory device or the like. The BIST is a test in which a test pattern is previously made inside a semiconductor chip and a test is conducted on all the memory cells in the chip using the test pattern, and whether or not there is a failure on the memory is output as information indicative of PASS or FAIL to the outside of the semiconductor chip.
The employment of such a test method by the BIST provides a merit of capability of conducting a memory test at a high speed. However, there is a problem that information obtained only concerns whether or not there is trouble on the memory, and it is impossible to obtain any information concerning where the trouble exists on the memory cell, at how many locations the trouble exists.
It is possible to specify the failure locations and the number of failures of the memory cells by adding registers for holding trouble information in accordance with the memory cells to a BIST circuit. However, this considerably increases the circuit size of the BIST. Thus, the larger BIST circuit is required to obtain the more pieces of trouble information. If no trouble occurs, the circuit which have been added to hold trouble information become needless.
FIG. 1 is a block diagram showing a configuration of a conventional memory BIST circuit including registers for holding trouble information as described above. As shown in FIG. 1, the memory BIST circuit comprises an address counter circuit 101 for outputting address information to specify a memory cell in a memory (RAM) 100, a data generator circuit 102 for generating an expected value of a test result, a comparator circuit 103 for comparing the output signal of the memory 100 with the expected value and determining whether the memory 100 is good or bad, and a BIST controller circuit 104 for controlling the state of the memory BIST operation.
The address counter circuit 101, the data generator circuit 102, and the comparator circuit 103 are individually controlled by the BIST controller circuit 104. The comparator circuit 103 has a function capable of holding the comparison result in a register by every bit-line. Therefore, an inspection of the state of the register makes it possible to specify at least failures on each bit-line. However, there is a problem that the failure location can not be specified in more detail because of the absence of a function of holding address information.
Meanwhile, a test method is conducted in which the output signals of all the memory cells and test addresses are output to an external terminal of the semiconductor chip and input to an exclusive memory tester or the like to be examined, but the problem thereof is impossibility of a test on the memory operating at a high speed. In other words, since the operating speed of the memory tester is low relatively to the operating speed of the memory, there is a limit to a test on a recent high speed memory by the exclusive memory tester.
A product mounting a plurality of memories on a semiconductor chip requires many selector circuits in order to give output signals of all the memory cells to an external terminal of the semiconductor chip. Therefore, the test circuit for the entire product increases in size, besides, there is a problem that the propagation speed of a signal decreases to affect the system operating speed of the product.
For the above reason, a failure analysis using the BIST method is performed as follows under the present circumstances. First, a memory test is conducted by the BIST method to determine the presence or absence of trouble on a memory subjected to the test. In this determination method, the memory output signal is compared with a previously prepared expected value, and when both values disagreement with each other, the register is allowed to store information indicative of xe2x80x9cpresence of trouble,xe2x80x9d and the information is output to the external terminal. The information thus obtained indicates only the presence or absence of occurrence of trouble.
When the occurrence of trouble is recognized, a failure analysis is then performed. In this failure analysis, the BIST operation is performed, and then the BIST operation is suspended when a trouble occurrence pattern is found. The circuit state is set such that information indicative of the failure location (bit-line/word-line information) at that time is output to the external terminal, thereby obtaining failure information.
However, in such a test method, it is necessary to repeat the BIST operation and the failure information detection operation to obtain the full failure information for a memory having a plurality of failures. Thus, sequentiality of the BIST operation is lost, resulting in the case in which the test result differs from the initial test result at the time of examining the presence or absence of trouble. Further, since it is not recognized in which pattern the trouble occurs, the BIST operation needs to be carried out to the last pattern to obtain the trouble information, which brings about a problem that it takes much time to detect the failure information.
The present invention is made to solve the above problems and its object is to specify the presence or absence, locations, the number, and the like, of failures, by one BIST test without addition of a complicated circuit configuration and to reduce considerably the processing time required for a memory test.
In an apparatus for analyzing a failure for a semiconductor memory device of the present invention, failure determination of the inside of the semiconductor memory device is made in sequence based on address information supplied to the semiconductor memory device using a test circuit of the semiconductor memory device, and resultant output failure determination information and the address information are fetched and held in a scan register circuit. This scan register circuit is made by using an originally provided logic scan circuit used at the time of conducting a test on a logic circuit other than the semiconductor memory device, and adding a function capable of obtaining failure determination result information thereto.
The present invention comprises the above-described technical means, thereby making it possible to use efficiently the scan register circuit originally existing for a logic test also for a memory test thereby to hold the failure determination result information detected upon the test of the semiconductor memory device in sequence into the scan register circuit with the address information. Accordingly, even if the present invention does not include an addition of a complicated circuit configuration, it becomes unnecessary to repeat processing of suspending the test operation at every detection of failure to specify the failure location, and it becomes possible to obtain information concerning one or more failure locations and the number of failures into the scan register circuit by one test.
Consequently, it is possible to obtain information concerning one or more failure locations and the number of failures by one test without addition of a complicated circuit configuration and to reduce considerably the processing time required for a memory test.